Clocks are an integral part of electronics. Their use is wide and diverse. Clocks are used for circuit control, to keep track of time, etc. Within the personal computer clocks are used by a variety of logic blocks including, but not limited to, for example, the central processor unit (CPU), as bus clocks, clocks for system chip sets, clocks for peripheral devices, such as but not limited to, disk drives, storage units, etc. Additionally they are used to synchronize events and provide a reliable source of a stable frequency.
For example, FIG. 3 illustrates an approach 300 showing clock generation and several system components. Here at clock chip 302 three clock signals 302-1 CPU clock, 302-2 PCK clock, and 302-3 SRC clock are generated and distributed to various components. CPU 304 receives CPU clock 302-1 and may communicate and/or generate clock signals via link 305 for use by the System Chip set 306. Additionally, the Clock chip 302 and system chip set 306 interface via link 307.
Often the speed of a system needs to be adjusted. Often this is accomplished by adjusting the clocks used by the system. For example, in FIG. 3 an External Trigger Event 308 may indicate that a change in system speed is needed. This may be communicated to the CPU 304 as an interrupt signal 309. In one implementation, the interrupt 309 causes the CPU 304 to be interrupted from its processing to effect a change in system speed. This may be accomplished, for example, by having the CPU 304 communicate via link 305 to the system chip set 306 then via 307 to effect a change in the clock chip 302 thereby affecting those clocks 302-1 through 302-3 possibly needing changing. The CPU 304 in one implementation will cause an I2C signal to be generated which will effect the changes needed in clock chip 302.
FIG. 4 illustrates one implementation 400 inside a clock chip showing two clocks being generated. At 402 is a reference clock which is communicated via link 403 to an M-divider block 404 whose output is communicated via 405 to Phase detector and Charge pump and VCO block 406. The output of the Phase detector and Charge pump and VCO block 406 is communicated via 407 to the CPU clock output divider 408 whose output 409 is communicated to a CPU. Block 406 output via 407 is also communicated to PCI clock output divider 410 whose output 411 is used by, for example, PCI circuits. Block 406 output via 407 also is communicated to N-divider 412 whose output 413 goes back into block 406. N-divider 412 is controlled by outputs communicated via 415 from a look up table (LUT) 414. LUT 414 is controlled by an input from an I2C control register 416 which is communicated to the lookup table via 417. M-divider 404 is controlled by outputs communicated via 419 from a look up table (LUT) 414. LUT 414 is controlled by an input from an I2C control register 416 which is communicated to the lookup table via 417. In this way the I2C can control the output frequency at, for example, 409 and 411.
In this implementation, the source of the I2C signals is created by the CPU, for example, 304 in FIG. 3. Thus the CPU which may be interrupted by an external trigger event 308 communicated by 309 to the CPU 304 will result in the CPU 304 generating the I2C signals which change system speed. In this implementation then, CPU resources are required to change the system speed and thus the CPU must process this request and therefore has fewer resources available for processing other task. This implementation then affects the available CPU resources by requiring it to generate signals required for changing system clocks.
FIG. 5 illustrates one implementation 500 inside a clock chip showing two clocks being generated. At 502 is a reference clock which is communicated via link 503 to an M-divider block 504 whose output is communicated via 505 to Phase detector and Charge pump and VCO block 506. The output of the Phase detector and Charge pump and VCO block 506 is communicated via 507 to the CPU clock output divider 508 whose output 509 is communicated to a CPU. Block 506 output via 507 is also communicated to PCI clock output divider 510 whose output 511 is used by, for example, PCI circuits. Block 506 output via 507 also is communicated to N-divider 512 whose output 513 goes back into block 406. N-divider 512 is controlled by outputs communicated via 519 from an I2C control register 516. M-divider 504 is controlled by outputs communicated via 521 from an I2C control register 520. In this way the I2C can control the output frequency at, for example, 509 and 511.
In this implementation, the source of the I2C signals is created by the CPU, for example, 304 in FIG. 3. Thus the CPU which may be interrupted by an external trigger event 308 communicated by 309 to the CPU 304 will result in the CPU 304 generating the I2C signals which change system speed. In this implementation then, CPU resources are required to change the system speed and thus the CPU must process this request and therefore has fewer resources available for processing other task. This implementation then affects the available CPU resources by requiring it to generate signals required for changing system clocks.
Thus, in one implementation when there is an external event that needs to change system clocks and/or speed (for example, CPU clock, PCI clock etc.), it has to interrupt the CPU from doing normal application programs. The CPU will stop its normal operation to send commands to the system chipset. The System chipset will then program the clock chip to change the speed by using the I2C bus. When the external event is finished, the CPU may be interrupted again to change back to the normal speed. This interrupting will slow down overall system performance. Additionally, sometimes the CPU may be executing a program which does not allowed for interruption. Additionally, the use of the I2C bus to effect this change may not be efficient. This presents a problem.
Additionally, clock chips may use three clock generators, for example, PLLs to generate three clocks. In a system this may force the sharing of clocks, for example the CPU and the SRC (serial reference clock used for PCI Express) may have to share the same clock frequency. In some applications the system may want to speed up, for example, the CPU without change the frequency of other circuits, like the SRC. This may not be possible in a three PLL clock generator where a common clock is shared. This presents a problem.